As integrated circuits become smaller, denser, and faster, development of new methods for testing and debugging has become necessary. In particular, the localization of defects or sensitive areas in circuits, which may contribute to or cause operational failures, is a critical element in debug and failure analysis, as well as enabling circuit repairs with charged particle tools such as focused ion beam (“FIB”) tools.
The use of lasers in the investigation of integrated circuit defects and sensitive areas is well known. When a laser beam impinges on a material such as a semiconductor substrate or metal interconnect, it can cause thermal effects and/or photo-generated charge carrier effects, both of which can be utilized to localize many types of circuit defects. Two methods, referred to as thermally induced voltage alteration (“TIVA”) and optical beam induced resistance change (“OBRICH”) were developed to utilize thermal effects for circuit defect analysis. Light induced voltage alteration (“LIVA”) is a method developed to utilize photo-generated charge carrier effects for circuit defect analysis. The TIVA method is described in U.S. Pat. No. 6,078,183 titled “Thermally-Induced Voltage Alteration for Integrated Circuit Analysis,” issued Jun. 20, 2000, the LIVA method is described in U.S. Pat. No. 5,430,305 titled “Light Induced Voltage Alteration for Integrated Circuit Analysis,” issued on Jul. 4, 1995, and the OBIRCH method is described in U.S. Pat. No. 5,804,980 titled “Method and System Testing an Interconnection in a Semiconductor Integrated Circuit,” issued on Sep. 8, 1998. These three patents are hereby incorporated by reference in their entireties.
In thermal laser stimulation, a laser beam, generally infrared, is scanned across the front side or backside of an integrated circuit at a constant rate in a raster pattern (i.e., a series of rows collectively defining a box) so as to locally heat the device under test (“DUT”), and to induce thermal gradients in such regions as the metal interconnects. A variety of measurements can be made, such as changes in voltage, current, power consumption, or resistivity as a result of the local heating caused by the beam. This facilitates localization of such defects as shorts, leakage sites, spikes, abnormal contacts or vias, and filaments, as well as sensitive areas which may include signal flow bottlenecks.
When a laser beam, generally visible or near-IR, and having a photon energy above the silicon band gap, impinges on a silicon substrate which may have an integrated circuit therein, a photo-generated charge carrier effect results. The laser beam energy is dissipated, in part, by generating electron-hole pairs in the silicon. In high-field regions such as transistor junctions, the electron-hole pairs dissociate, resulting in a measurable current generation. Measurement of this current can enable localization of defective junctions, and junctions connected to defects.
Prior methods of utilizing the aforementioned techniques to measure current or voltage variations or device parameter variations resulting from laser-induced heating or photo-generated charge carriers for defect mapping employ a laser source and a testing unit which is not synchronized with the laser source. The testing unit, such as an automatic test equipment (“ATE”) device, applies a test pattern, typically in the form of a series of vectors or logical 1s and 0s to one or more input pins of a DUT, and collects the resulting output pattern from the DUT. The output pattern may be compared to an expected pattern to derive a pass/fail indicator. For a first example, in the prior method known as “static fault mapping”, the DUT is held at a particular internal state by stopping the tester generating the test pattern at a certain vector of interest while a laser beam scans an area of the device and current or voltages are measured. Defects or sensitive areas are located by determining where large current or voltage changes are seen to be induced by the beam. However, devices such as dynamic logic devices generally cannot be held in a static state sufficiently long for the scanning and measurement to be completed.
For a second example, in the prior method known as “soft error mapping” or “soft defect localization,” soft errors (i.e., test failures due to device or circuit errors, which can be induced by adjusting test parameters such as clock speed or power supply voltage), are located by scanning an area of a device with a continuous heating laser beam, or perhaps a current-inducing laser beam, while running a test pattern and observing the pass/fail signal from the device tester. As with the static fault mapping method, the laser source is not synchronized with the testing unit. To avoid ambiguities in the results, the dwell time of the laser beam at each XY position (pixel) in the raster scan pattern is generally set to be at least as long as the time for a complete test pattern to run. Although the XY location of the current elements causing the soft error can be located using this method, the actual test vector or vectors exercising the soft error are not identified. Descriptions of the soft-defect localization method are found in a paper titled “Soft Defect Localization (SDL) on ICs” by Michael R. Bruce et al., Proceedings from the 28th International Symposium for Testing and Failure Analysis, 3–7 Nov. 2002, Phoenix, Ariz.; U.S. Pat. No. 6,549,022 titled “Apparatus and Method for Analyzing Functional Failure in Integrated Circuits,” issued Apr. 15, 2003; and U.S. Pat. No. 6,483,326 titled “Localized Heating for Defect Isolation During Die Operation,” issued Nov. 19, 2002, all of which are hereby incorporated by reference in their entireties.
The utility of laser-enhanced defect- and fault-, sensitive area- or error-mapping would be greatly enhanced by an apparatus and method enabling the use of synchronous timing of the laser with respect to the test pattern, as a controlled variable.